1. Field of the Invention
This invention is related to the field of circuits for handling multiple possible drivers of a line.
2. Description of the Related Art
In circuit design, there are many uses for a line (or buses comprising multiple lines) which may have multiple drivers of the line. Generally, one of the drivers may drive the line at any given time. For example, memory arrays such as caches may employ such a structure for each bit read from the memory array. The memory array may include multiple banks, one of which may be read at any given time. Each bank has an output that may drive the line corresponding to the bit, and the bank that is being read drives the line. As another example, communication lines between two or more circuits may be driven by any of the circuits according to some protocol (often referred to as bi-directional lines, since the lines may be inputs or outputs of a given circuit at a given point in time).
FIG. 1 illustrates a first prior art circuit providing for multiple drivers of a line (the line is illustrated as carrying a Dout signal in FIG. 1, and may be referred to herein as the Dout line). The circuit of FIG. 1 may sometimes be referred to as a low swing, dual rail dynamic circuit. Each driver may drive a dynamic data signal and its complement (e.g. the dynamic data signal d0 and its complement d0# may be driven by a first driver and the dynamic data signal d1 and its complement d1# may be driven by a second driver). In FIG. 1, the dynamic data signals are precharged low and conditionally evaluate high dependent on whether or not the driver is driving a value and whether or not the value is a logical one or a logical zero. At most one driver may be permitted to drive its dynamic data signals at any given evaluation of the Dout signal. For example, the driver corresponding to the dynamic data signals d0 and d0# may drive the line. If the value being driven is a logical one, the d0 dynamic data signal may assert. If the value is a logical zero, the d0# dynamic data signal may assert. Each dynamic data signal is coupled to the gate of an n-type metal oxide semiconductor (NMOS) transistor which is further coupled to one of two bit lines (bit and bit#). The bit and bit# lines are precharged to Vdd using the PMOS transistors coupled to the precharge signal Pchg. One of the bit and bit# lines may be conditionally discharged by an NMOS transistor receiving an asserted dynamic data signal. A pair of PMOS transistors having gates coupled to bit and bit# lines and coupled to the opposite bit or bit# line may actively hold the precharge on the bit or bit# line which is not discharged by the NMOS transistors, responsive to the discharge of the bit or bit# line to which its gate is coupled. A sense amplifier (SA) is coupled to the bit and bit# lines and senses the differential between the two lines (responsive to the clock input SACLK) to generate the output line (Dout). Two additional NMOS transistors may be added for each additional driver (having gates coupled to receive the dynamic data signal and its complement from that driver).
FIG. 2 illustrates a second prior art circuit which may be used to handle multiple drivers of a line (Dout). The circuit of FIG. 2 may sometimes be referred to as a single-rail dynamic circuit. In FIG. 2, each driver may drive a dynamic data signal (e.g. the dynamic data signal d0 may be driven by a first driver and the dynamic data signal d1 may be driven by a second driver). Similar to FIG. 1, the dynamic data signals are precharged low in this embodiment and conditionally evaluate high if the corresponding driver is driving Dout and the value being driven is a binary one. Each dynamic data signal is coupled to the gate of an NMOS transistor, which discharges the internal node N1 in response to the dynamic data signal asserting. A precharge PMOS transistor is coupled to the node N1 and precharges the node N1 to Vdd responsive to the precharge signal Pchg. An inverter is coupled between the node N1 and the output Dout, and a feedback PMOS transistor has a gate terminal coupled to Dout and coupled to the node N1 to maintain the precharge state if the NMOS transistors do not discharge the node N1. Thus, an output Dout of binary zero is supplied via the precharge if there are no drivers or if the driver is driving a binary zero (and thus does not assert its dynamic data signal). An output Dout of binary one is supplied if the driver is driving a binary one (and thus asserts its dynamic data signal). Each additional driver may be handled by adding an NMOS transistor in parallel with those shown in FIG. 2 and coupled to receive the dynamic data signal from the additional driver.
FIG. 3 illustrates a third prior art circuit which may be used to handle multiple drivers of a line (Dout). The circuit of FIG. 3 may sometimes be referred to as a static push/pull circuit. The circuit of FIG. 3 takes static inputs (the complement of the data being driven, d0# or d1#, and a select line sel0 or sel1) from each potential driver of the line. The driver of the line asserts its select line sel0 or sel1 and provides the data to be driven on the complement data signal d0# or d1#. The first driver (d0# and sel0) is handled via a NAND gate 10, a PMOS transistor 12, a NOR gate 16, and an NMOS transistor 18. The NAND gate 10 is coupled to receive the sel0 signal and the d0# signal, and is coupled to the gate of a PMOS transistor 12, which is coupled to the input of an inverter 14. The NOR gate 16 is coupled to receive the sel0 signal (on an inverting input) and the d0# signal, and is coupled to the gate of the NMOS transistor 18, which is coupled to the input of the inverter 14. If the d0# signal is a one (the data is a zero) and the select signal is a one, the NAND gate 10 activates the PMOS transistor 12, driving the input of the inverter 14 to a one and thus Dout to a zero. If the d0# signal is a zero and the select signal is a one, the NOR gate 16 activates the NMOS transistor 18, driving the input of the inverter to a zero and thus Dout to a one. If the select line is a zero, then neither of the PMOS or NMOS transistors 12 or 18 is activated. A similar circuit handles the second driver (d1# and sel1), and additional circuits may be added to handle additional drivers.
FIG. 4 illustrates a fourth prior art circuit which may be used to handle multiple drivers of a line (Dout). The circuit of FIG. 4 may sometimes be referred to as static tristate inverters. A first tristate inverter corresponds to the first driver (d0 and sel0) and includes PMOS transistors 20 and 22 in a stack and NMOS transistors 24 and 26 in a stack. The PMOS transistor 20 has its gate coupled to the d0 signal, while the PMOS transistor 22 has its gate coupled to receive the inverse of the sel0 signal. The NMOS transistor 24 has its gate coupled to receive the sel0 signal, and the NMOS transistor 26 has its gate coupled to the d0 signal. Essentially, the transistors 22 and 24 activate if the sel0 signal is asserted, and one of the transistors 20 or 26 activates in response to the data signal d0. Thus, either a binary zero is driven on Dout by transistors 20 and 22 through the inverter 28 if the sel0 signal is asserted and d0 is a zero, or a binary one is driven on Dout by transistors 24 and 26 through the inverter 28 if the sel0 signal is asserted and d0 is a one. If the sel0 signal is deasserted, then the tri-state inverter does not drive the inverter 28. A similar circuit is used for the second driver (d1 and sel1), and additional circuits may be added to handle additional drivers.
In one embodiment, an apparatus includes at least a first transistor, a second transistor, and a circuit. The first transistor has a first control terminal coupled to receive a first dynamic data signal, and is coupled to a first node. The first transistor is configured to drive a first state on the first node responsive to an assertion of the first dynamic data signal. The second transistor is coupled to the first node and has a second control terminal. The second transistor is configured to drive a second state on the first node responsive to a signal on the second control terminal. The circuit is coupled to generate the signal on the second control terminal and is coupled to receive a second dynamic data signal. The second dynamic data signal is a complement of the first dynamic data signal, wherein the circuit is configured to activate the second transistor responsive to an assertion of the second dynamic data signal.
A memory array may include a plurality of banks of memory, each bank configured to output a first dynamic data signal indicative of a bit stored in the bank and a second dynamic data signal indicative of the complement of the bit. The memory array may further include a bank select circuit coupled to receive the first dynamic data signal and the second dynamic data signal from each of the plurality of banks and configured to output a selected bit responsive to the first dynamic data signal and the second dynamic data signal from each of the plurality of banks. The bank select circuit comprises a first plurality of transistors, each having a control terminal coupled to receive the first dynamic data signal from a respective one of the plurality of banks. Each of the first plurality of transistors is coupled to a first node and is configured to drive a first state on the first node responsive to an assertion of the first dynamic data signal. A second transistor is coupled to the first node and has a second control terminal. The second transistor is configured to drive a second state on the first node responsive to a signal on the second control terminal. Coupled to generate the signal on the second terminal and coupled to receive the second dynamic data signal from each of the plurality of banks, a circuit is configured to activate the second transistor responsive to an assertion of the second dynamic data signal from one of the plurality of banks.